This invention relates generally to semiconductor chip package assembly, and in particular to wire bonding package assembly. More specifically, the invention relates to lead frame packages having low-K Si dice applied with molding interface materials and corresponding methods for their assembly.
As advances in semiconductor technology increase the speeds of integrated chips (dice), a shift towards using dice with a plurality of layers of low dielectric constant (low-K) materials have been sought. Such low-K materials assist in the reduction of propagation delay, thereby improving the electrical performance of low-K Si dice. However, low-K Si dice have also presented significant packaging problems for incorporation in conventional wire bonding packages.
One such problem is that during the manufacture, industrial grade reliability testing (e.g., as provided by Electronic Industries Association—EIA or Joint Electron Device Engineering Council—JEDEC), or field use of these low-K Si dice in conventional wire bonding packages, the low-K Si dice may experience substantial amounts of damaging mechanical stress (e.g., tensile stress; shear stress) resulting from the construction of the packages themselves. This is because depending on the amounts of temperature cycling that the packages experience and the differences in the coefficient of the thermal expansion (CTE) of the various package components (e.g., molding compound, wire bonding packaging substrate, low-K Si die, etc.), the resulting mechanical stress (herein referred to as “package stress”) generated within the package may be large enough to crack, delaminate, or collapse any layer of the low-K materials in the dice. For example, cracks will initiate in the low-K material layers during reliability thermal cycle testing and especially during industrial grade testing that ranges from −55° C. to 125° C. As such, the reliability and operability of these low-K Si dice can be substantially compromised and impaired. Furthermore, since low-K materials are structurally brittle, their susceptibility to the damaging effects of these stresses is even greater than other dielectric materials (e.g., silicon dioxide).
In controlling these package stresses, many factors must be considered. Of particular significance, however, is the interplay between the low-K Si die and the molding material (i.e., molding compound) used to form the molding cap of the wire bonding package. Since the molding compound is used to couple together the various components (e.g., electrical contacts, substrate, die attach pad, die, etc.) of the wire bonding package, the molding compound plays a significant part in transferring the stress from other parts of the wire bonding package (as well as from itself) to the low-K Si die and vice versa. In order to minimize the amount of stress transferred, one approach is to use a molding compound having a low modulus and low CTE that is closer to that of the low-K Si die.
Although the described approach may provide satisfactory results in some cases, there are continuing efforts to provide further improved low-K Si die wire bonding packages and packaging methods that control the package stresses induced onto the low-K Si die and that provide industrial grade reliability thereof for incorporating into electronic devices.